1. Field of the Invention
The present invention relates generally to a semiconductor package, and more particularly to a flip chip bonded package applicable to a fine pitch technology.
2. Description of the Prior Art
As generally known in the art, the semiconductor packaging technologies have been developing towards mounting a greater number of packages on a substrate of a limited size, thereby reducing the overall size of the packages. For example, various types of chip size packages (hereinafter referred to as “CSPs”) have been developed to reduce the size of semiconductor chips to at least 80% of the overall size of the packages. In general, the CSPs are considered more advantageous in that than other types of the conventional semiconductor packages, because the CSPs allow a greater number of packages to be mounted on a substrate of a limited size, thereby realizing more compact and high-capacity semiconductor memory product.
In addition to reducing the size of packages, recent packaging technologies are also directed to mounting 2-4 semiconductor chips in a single package for higher capacity.
The CSPs and stack packages are generally mounted on a substrate during fabrication, and a wire bonding process is used to electrically connect semiconductor chips to the substrate.
However, when wire bonding is used for electrical connection inside a package, the bonding wires could be cut off or severed in a subsequent molding process. In addition, the package size is reduced by the loop of the bonding wires, as well as by their length. Particularly, the length of signal transmission paths in a package using wire bonding is determined by the length of the bonding wires. This makes it difficult to secure the desired electrical properties of the package.
In an attempt to solve these problems, a conventional flip chip bonding technology has been proposed, in which the semiconductor chips are connected to a substrate using bumps. According to the flip chip bonding technology, semiconductor chips are mechanically attached to a substrate via bumps, which are formed on the bonding pads of the semiconductor chips, while being electrically connected to electrodes on the substrate.
More specifically, FIG. 1 is a cross-sectional view showing a conventional flip chip bonded package. Referring to FIG. 1, a semiconductor chip 10 is attached to a substrate 20 via solder bumps 14, which are formed on a bonding pad 12 of the semiconductor chip 10, while being electrically connected to electrodes 22 on the substrate 20 by the solder bumps 14. A filler 30 is used to underfill the space between the semiconductor chip 10 and the substrate 20. Solder balls 40 are attached to ball lands 24 on a lower surface of the substrate 20 so that the package can be mounted on an external circuit via the solder balls 40. In FIG. 1, reference numeral 26 refers to solder resist.
The flip chip bonded package, to which the flip chip bonding technology has been applied, has a smaller package height than in the case of using a wire bonding technology, because solder bumps are used for electrical and mechanical connection. Furthermore, shorter signal transmission paths improve the electrical properties.
However, in the case of a conventional flip chip bonded package, the substrate must have electrodes (such as FIG. 1, element 22), which correspond to the solder bumps one by one, for the purpose of electrical connection. When the electrodes have a narrow pitch, it is difficult to define the photoresist for plating the solder bumps. This increases the possibility of a short circuit occurring between the solder bumps.
In order to avoid these problems, it is necessary to modify the substrate design or perform expensive processes. In addition, the bonding pads must be rearranged on the chips in an inefficient manner. This increases the cost for manufacturing products and degrades the competitiveness.